The invention relates to electronic packages and more particularly to such packages which utilize circuitized substrates and semiconductor devices (chips) as part thereof. Even more particularly, the invention relates to such electronic packages for use in the information handling (computer) field.
Thin film electronic packaging structures are known in the art including, for example, those shown and described in U.S. Pat. No. 4,849,856 (Funari et al), U.S. Pat. No. 4,914,551 (Anschel et al), U.S. Pat. No. 4,962,416 (Jones et al) and U.S. Pat. No. 4,965,700 (McBride). See also U.S. Pat. No. 5,057,969 (Ameen et al), U.S. Pat. No. 5,115,964 (Ameen et al), U.S. Pat. No. 5,133,495 (Angulas et al) and, U.S. Pat. No. 5,203,075 (Angulas et al) for related structures. Such packaging structures, as defined in these patents, typically utilize at least one thin film, flexible circuitized substrate as part thereof. Thin film flexible circuitized substrates as produced today possess several distinct advantages (e.g., high density, flexibility, relative ease of manufacture, etc.) desired in the information handling systems. Typically, such circuitized substrates include a thin dielectric (e.g., polyimide) layer having at least one circuit layer thereon. Such thin film, flexible circuitized substrates may be positioned on and electrically coupled to another circuitized substrate (e.g., printed circuit board) to thereby electrically couple a chip, which is connected to respective portions of the thin film circuitized substrate""s circuitry, to corresponding circuitry on the printed circuit board. The aforementioned U.S. Pat. Nos. 4,849,856, 4,914,551, 4,962,416 and 5,057,969 illustrate representative examples of such packaging structures which utilize this means of connection.
In U.S. Pat. No. 5,561,323 (Andros et al), there is described a substrate including at least one solder element which is positioned in electrical contact with a plated through hole (PTH). The solder element is bonded to the PTH by solder reflow forming a solder connection wherein the solder ball is aligned with the PTH and the PTH is brought in physical contact therewith, following which heat is applied to cause at least partial melting of the solder ball and capillary movement or the like of such solder through the respective openings. It is possible to provide solder elements for each of several PTHs in the substrate where each of the solder elements is bonded to the respective PTH by the solder reflow operation described to form a pattern of solder connections to thereby electrically couple a chip thereon.
As understood from the following, the invention is able to readily utilize such flexible circuitized substrates in combination with a capillary soldering technique to produce a resulting electronic package structure of relatively high density. The invention is also able to be used to produce a number of different (multi-chip module or MCM) structures heretofore unknown in the art.
Multi-chip modules (MCMs) are well known in the art and provide many advantages, including that of allowing individual chips to be located very close to one another, thereby reducing chip-to-chip interconnection links. A multi-chip module is comprised of a chip carrier substrate on which various chips are positioned and on which the chip terminals extend out by various means to terminals spaced to suit the spacing and dimension of wires on the next higher level of package (i.e., card or board). The multi-chip module will usually contain multilevel wiring planes and power planes interconnecting several of its chips. The multi-chip package is capable of supporting several chips on a single package, where the chip carrier substrate can be a material such as a ceramic, silicon, or a laminate such as a common printed circuit board laminate material. Such materials include polyimide, glass epoxy or polytetrafluoroethylene.
Manufacture of such multi-level chip carrier substrates using conventional techniques has a number of disadvantages. Conventional multi-level substrate processing frequently comprises a sequential process in which one circuit is laid down upon and formed over an earlier formed circuit with suitable dielectric layers to isolate the several circuit layers from one another. Such substrates may employ many layers, each of which, excepting only the last, effectively forms a base upon which the next layer is constructed. The multi level substrate, therefore, can be effectively tested only after completion of all of its layers. This may be expensive because many layers of a module made without defects may have to be discarded if a final layer is found to be faulty, or one may continue to add value to a faulty product.
As defined herein, the electronic package of the present invention represents a compact structure with two flexible circuitized substrates electrically coupled together by a solder member. The structure can serve as a single chip carrier which can be electrically coupled to a circuit board to allow communication of the chip to the outside environment through the circuit board. The invention can also be adapted for use as part of a high circuit density multi-chip module. Furthermore, the package as defined herein is capable of providing high power dissipation and excellent electrical performance in a structure that can be assembled in a relatively facile and inexpensive manner. Additionally, the electronic package of the present invention substantially reduces waste in manufacture because individual circuitized substrates used in the multi-chip module manufacture can be individually tested prior to assembly. Even further, the structure as defined herein is adapted for accepting a variety of different chip configurations and associated circuitized substrate structures, thus providing a much desired versatility for such a package.
It is believed that an electronic package possessing the features mentioned above, and others discernable in the teachings provided herein, represents a significant advancement in the electronic packaging field. It is also believed that a new and unique method for making such a package would constitute a significant contribution to this field.
It is, therefore, a primary object of the invention to enhance the art of electronic packaging by providing an electronic package possessing the several advantageous features defined herein.
It is another object of the invention to provide a method of making such an electronic package.
In accordance with one aspect of the invention, there is defined an electronic package which comprises a first circuitized substrate having an external surface and at least one conductive aperture. The electronic package also includes a second circuitized substrate having at least one conductive aperture therein and an external surface. The first and second circuitized substrates are aligned such that the at least one conductive aperture of the first circuitized substrate is substantially aligned with the at least one conductive aperture of the second circuitized substrate. The electronic package further includes at least one solder member having a first contact portion extending from the external surface of the first circuitized substrate and a second contact portion extending substantially within both of the aligned conductive apertures of the first and second circuitized substrates to secure the circuitized substrates together.
In accordance with another aspect of the invention, there is defined a method of making an electronic package wherein the method comprises the steps of providing a first circuitized substrate having an external surface and at least one conductive aperture therein, the at least one conductive aperture in contact with the external surface and providing a second circuitized substrate having at least one conductive aperture therein and also having an external surface. The next step comprises aligning the circuitized substrates such that the at least one conductive aperture of the first circuitized substrate is substantially aligned with the at least one conductive aperture of the second circuitized substrate. The next step comprises forming at least one solder member including a first contact portion extending from the external surface of the first circuitized substrate and a second contact portion extending substantially within both of the aligned conductive apertures of the first and second circuitized substrates, the solder member securing the substrates together.